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The AI wave is reshaping the entire electronic circuit industry chain. High-speed PCBs, semiconductor substrates, packaging substrates, thermal materials, and the global market landscape are all undergoing unprecedented changes. On October 28-29, the 2026 China-Japan Electronic Circuits Autumn Conference and Autumn PCB Technology/Information Forum will be held at the Shenzhen World Exhibition & Convention Center · Bao'an New Hall. The conference is jointly hosted by the China Printed Circuit Association (CPCA) and the Japan Electronics Packaging and Circuits Association (JPCA), with the theme "Innovation-Driven Chips, Intelligent Computing Future," bringing together industry associations, research institutes, leading enterprises, and frontline technical experts from both countries to jointly explore new paths for the PCB industry in the AI era. The keynote forum of this conference will be held on October 28 in Mangrove Hall A, 2nd Floor, West Side of the South Registration Hall of the exhibition center. Five heavyweight guests will share their insights on core topics such as AI computing power, semiconductor substrates, thermal materials, and market trends.   From trend analysis to technology implementation, a collision of ideas covering the entire industry chain. This keynote forum is not a single technology sharing session, but a complete industry chain exchange:   looking at industry trends—how AI is changing the pace of development of the electronic circuit industry;   looking at material breakthroughs—how copper-clad laminates, semiconductor substrates, and thermal interface materials support higher computing power;   looking at technology implementation—how high-density packaging, high-speed transmission, and thermal management are moving toward industrialization;   looking at the market landscape—what new opportunities and new challenges the global PCB industry chain faces in the AI era. Whether you come from PCB manufacturing, materials, equipment, packaging, end applications, or investment research, you can find key clues for judging the direction of the industry in this keynote forum.   Conference Information 📅 Conference Time: October 28-29, 2026 📍 Conference Venue: Shenzhen World Exhibition & Convention Center · Bao'an New Hall, No. 1 Zhan Cheng Road, Fu Hai Street, Bao'an District, Shenzhen 🎯 Conference Theme: Innovation-Driven Chips, Intelligent Computing Future Hosts: China Printed Circuit Association (CPCA), Japan Electronics Packaging and Circuits Association (JPCA) Organizer: CPCA Science and Technology Working Committee Media Support: Printed Circuit Information Magazine, PCB Information Network   --------------------------- Source: CPCA Disclaimer: We respect originality and also value sharing; the copyright of text and images belongs to the original authors. The purpose of reprinting is to share more information, which does not represent the position of this account. If your rights are infringed, please contact us immediately for deletion. Thank you.

As AI chips evolve toward large-size, high-density packaging, global giants are exploring glass substrates, with domestic materials and equipment companies participating in tandem, and the industrial layout now covering multiple segments. Intel publicly outlined its glass substrate roadmap in 2023, and its EMIB and Foveros packaging platforms provide a foundation for the collaborative development of new substrate materials and packaging structures. In July 2026, Lens Technology and Intel signed a TGV cooperation memorandum, with discussions covering glass through-holes, laser processing, metallization, and multilayer interconnection. Among other industry giants, media reported in September 2026 that Nvidia is evaluating glass substrates, as HBM and high-speed interconnection bring new substrate requirements. TSMC is developing CoPoS panel-level packaging and has publicly announced trial line plans, with square panels expected to improve area utilization efficiency in large-size packaging. Samsung Electro-Mechanics has demonstrated micro-via, metal filling, and precision processing technologies, and has formed a joint venture with Dongwoo Fine-Chem for glass core business; in October, media reported that it is conducting packaging-level reliability testing in conjunction with customer chips. The midstream processing segment offers the greatest value increment, and Lens Technology's experience in consumer electronics glass manufacturing provides a foundation for controlling dimensional precision, surface quality, and batch consistency. The company has disclosed progress in hole formation, seed layer deposition, electroplating via filling, and multilayer RDL processes, and is carrying out joint development and validation with North American customers; its memorandum with Intel also makes it one of the clearer cases among A-share companies of industrial collaboration with advanced packaging customers. On the domestic supporting side, on the equipment front, DR Laser and HGTECH are laying out TGV laser processing, Dongwei Technology is advancing electroplating and deposition equipment, and Tiancheng Technology is developing chemicals required for metallization and via filling. As customer validation deepens, upstream and downstream collaboration will jointly influence the pace of industrialization.   -------------------------------------------------- Source: Securities Market Weekly Disclaimer: We respect originality and also value sharing; the copyright of text and images belongs to the original authors. The purpose of reprinting is to share more information, which does not represent the position of this account. If your rights are infringed, please contact us immediately for deletion. Thank you.

On September 12, Hongchang Electronic Materials Co., Ltd. (hereinafter referred to as "Hongchang Electronic") released a private placement plan announcement, proposing to raise no more than 1.8 billion yuan for high-end copper clad laminate, prepreg, and advanced packaging film material (GBF) projects, stepping up investment in core printed circuit board (PCB) substrate materials required for AI servers and data centers. According to the plan disclosed this time, Hongchang Electronic's raised funds will be used for three major projects and to supplement working capital. It plans to invest 1.055 billion yuan (RMB, same below) in a project with an annual output of 13.2 million sheets of high-end copper clad laminate and 31.2 million meters of prepreg at its wholly-owned grandchild company Zhuhai Hongren Electronic Materials Technology Co., Ltd.; invest 95 million yuan in an intelligent and green upgrading and renovation project with an annual output of 9.6 million meters of high-end prepreg at its wholly-owned subsidiary Wuxi Hongren Electronic Materials Technology Co., Ltd.; invest 320 million yuan in an advanced packaging film material project, with the remaining funds used to supplement working capital. "The company has been deeply engaged in the field of electronic-grade resins and copper clad laminates for many years and has formed a complete industrial chain of 'electronic-grade resins - prepreg - copper clad laminate.' With the explosive growth driven by the rapid deployment of downstream fields such as AI computing infrastructure, the company needs to accelerate the layout of high-end product production capacity reserves to undertake growing high-end market demand, enhance its industry position, and cultivate new performance growth points," a relevant person from the securities department of Hongchang Electronic told a Securities Daily reporter. Hongchang Electronic's investment move is not an isolated case. Wind data shows that since the second half of this year, in addition to Hongchang Electronic, at least three other listed companies in China's copper clad laminate industrial chain have successively disclosed announcements on capacity expansion and new project implementation, collectively betting on the high-end computing materials track, reflecting the trend of structural upgrading and accelerated development in the copper clad laminate industry under the wave of AI computing power. In early August this year, the Kingboard (Jiangxi) New Materials Industrial Park project under Kingboard Laminates Holdings Limited (hereinafter referred to as "Kingboard Laminates"), a Hong Kong-listed company, officially broke ground at the Ganxiang Cooperation Industrial Park in Shangli County, Pingxiang City, Jiangxi Province. The project has a total investment of 3 billion yuan and is planned to be built in two phases, with the first phase involving an investment of about 1 billion yuan. Kingboard Laminates believes that with the vigorous development of artificial intelligence servers, supercomputing clusters, high-level intelligent driving, and new energy vehicle electronics, PCB requirements for underlying high-frequency, high-speed, high-heat-dissipation, and high-reliability copper clad laminates and upstream core materials such as electronic glass fiber cloth and copper foil have significantly increased. The project will deeply leverage the parent company's technological accumulation and high-end production capacity layout in the AI computing power and automotive electronics tracks, helping to alleviate the supply-demand gap for high-end computing substrate materials. In late July, the second factory project of Guangdong Shengyi Technology Co., Ltd. (hereinafter referred to as "Shengyi Technology"), a leading copper clad laminate enterprise, located in Dongguan Songshan Lake with a total investment of about 5.2 billion yuan, officially started construction. The project focuses on frontier fields such as high-frequency and high-speed materials for AI servers, smart automotive electronic substrate materials, and high-end packaging substrate materials. After completion, it will produce 48 million square meters of high-performance copper clad laminate and 100 million meters of commercial bonding sheet annually, and is expected to be put into operation successively in the second half of 2027. On July 22, Jin'an Guoji Group Co., Ltd. issued an announcement stating that after friendly negotiations with the People's Government of Jinwan District, Zhuhai City, the two parties reached a cooperation intention on matters related to the company's capital increase and production expansion project in Jinwan District, Zhuhai City, and signed the "Jin'an Guoji Capital Increase and Production Expansion Project Investment Agreement." The intended investment of the project is about 2 billion yuan, building an annual output of 20 million sheets of copper clad laminate and 40 million meters of prepreg for sale. Prismark, a globally renowned market research and consulting company in the electronics industry, predicts that the global copper clad laminate market will be about 24.2 billion US dollars in 2026, up 29.4 percent year on year; among which high-speed copper clad laminate will be about 9.5 billion US dollars, up 52.6 percent year on year. "The prosperity of this round of the copper clad laminate industry is not a simple cyclical rebound, but a structural upgrading opportunity brought about by the iteration of AI computing power. In the past, industry growth mainly came from consumer electronics and traditional communications, but the current focus of demand has shifted to computing infrastructure such as AI servers and high-speed switches, imposing higher technical thresholds on the dielectric performance, signal loss, and heat resistance stability of copper clad laminates, and there is a supply gap for high-end materials. Domestic manufacturers need to continue investing in production line transformation, product certification, and new material research and development, and an integrated layout across the entire industrial chain will create stronger competitive advantages," Qiu Sisheng, chief economist of Shenzhen Wanzhong Management Consulting Co., Ltd., told a Securities Daily reporter. --------------------------------- Source: Securities Daily Disclaimer: We respect originality and also value sharing; the copyright of text and images belongs to the original authors. The purpose of reprinting is to share more information, which does not represent the position of this account. If your rights are infringed, please contact us immediately for deletion. Thank you.

According to a report by Taiwan's Economic Daily News, materials manufacturer Nan Ya Plastics Corporation (hereinafter referred to as "Nan Ya Plastics") will significantly increase prices for copper clad laminate (CCL) and substrate materials starting in September. The market estimates that the price increase will range between 5% and 10%. According to a price adjustment notice from Nan Ya Plastics circulating in the market, the document states that recent sustained price increases in raw materials such as copper foil, fiberglass fabric, and resin have led to a substantial rise in CCL production costs. Although Nan Ya Plastics has tried to absorb the costs internally, the magnitude of the cost increase has been too great. To reflect these higher costs, the company will moderately adjust some of its selling prices, with substrate and base material prices each rising by 20%, effective September 1. In response to market rumors, Nan Ya Plastics officially stated that in order to cope with rising costs across various materials, the company has indeed been continuously negotiating with customers and gradually raising product prices since the beginning of this year. Overall, the cumulative increase for various electronic materials products this year ranges between 50% and 100%, but the extent of price adjustments varies by product due to differences in specifications, costs, supply and demand, and other factors. Nan Ya Plastics emphasized that the company has always negotiated and discussed prices with individual customers on a case-by-case basis, and does not unilaterally issue price increase notices, nor has it ever announced a one-time, unilateral 20% price hike. Therefore, the price adjustment letter circulating in the market is not an official notice issued by the company to its customers, and is speculated to be correspondence from the negotiation process with a specific customer. However, Nan Ya Plastics confirmed that multiple products will indeed see price increases starting in September, with the market generally estimating the hikes to be between 5% and 10%. In terms of the electronic materials product market, Nan Ya Plastics stated that among all materials, fiberglass fabric is currently facing the most severe shortage, with copper foil supply also in a similar situation. This has in turn driven up both the material and manufacturing costs of CCL. Nan Ya Plastics also recently noted that the four major U.S.-based cloud service providers (CSPs) are expanding their capital expenditures, which has driven the upstream electronic materials sector to face structural shortages and price increases. Nan Ya Plastics has been gradually raising prices on electronic materials to reflect these costs. In the fiberglass yarn segment, due to tight supply of electronic-grade fine yarn, low dielectric constant, and low coefficient of thermal expansion specialty fiberglass, Nan Ya Plastics has not only increased relevant production capacity in response to market demand but has also raised prices. In the fiberglass fabric segment, prices have also been adjusted upward due to capacity enhancements and increased sales growth of low thermal expansion coefficient fabric types. --------------------------------------------- Source: Xin Zhi Yuan (Chip Insights) Disclaimer: We respect originality and value sharing; the copyrights of text and images belong to their original authors. This reprint is intended for sharing more information and does not represent the views of this account. If your rights are infringed upon, please contact us promptly and we will remove the content at the earliest opportunity. Thank you.

According to Caixin News, the booming AI server market has driven a surge in demand for upstream PCB substrates, with domestic electronic yarn and electronic cloth supply-demand dynamics remaining tight and inventories nearly depleted. In the first half of this year, the industry has already undergone five rounds of price hikes. As of late August, the average price of G75 electronic yarn had surged 53% from the end of May, while mainstream 7628 electronic cloth posted a monthly increase of 17%-18%, with prices doubling from the beginning of the year. Ultra-thin and extremely thin specialty electronic cloths have seen price increases exceeding 140% year-to-date.   The current price surge in electronic yarn/cloth is driven by the combined forces of explosive structural demand from AI computing and rigid supply-side shortages.   On the demand side, the layer count of AI server PCBs has increased significantly, with high-end electronic cloth usage per unit rising 3 to 8 times compared to traditional servers. This is further supported by baseline demand from consumer electronics and automotive PCBs, collectively expanding the market.   On the supply side, leading manufacturers have actively curtailed production of conventional electronic cloth, reallocating capacity toward higher-margin ultra-thin and high-frequency specialty cloths, thereby exacerbating supply constraints for standard specifications. Coupled with strict controls on new kiln additions in the earlier period—and new production lines requiring up to two years to build—short-term capacity cannot be released, leaving the industry's near-zero inventory and tight supply-demand balance unlikely to ease in the near term.   High-end Q-cloth, in particular, has emerged as the core incremental segment in the industry, with technical barriers and profitability far exceeding those of traditional electronic cloth. Q-cloth features ultra-low dielectric constant and dissipation factor, significantly enhancing high-frequency signal transmission efficiency—making it ideally suited for next-generation AI servers, 1.6T/3.2T optical modules, and high-end switch computing hardware. Its usage per unit is 5 times that of traditional servers.   Currently, the global Q-cloth supply has long been monopolized by Japanese companies. However, domestic manufacturers are accelerating technological breakthroughs, with some having already completed customer qualifications and achieved small-volume shipments, paving the way for future mass production scaling.   Looking ahead, with the traditional peak season for the electronics industry in the second half of the year, combined with continued AI infrastructure buildout, electronic yarn/cloth prices are expected to maintain their upward trajectory, reinforcing the industry's volume-and-price dual-growth pattern. In the medium to long term, with new capacity releases lagging behind demand, the industry's high-prosperity cycle is likely to persist.   Institutions project a supply-demand gap of 113 million meters for standard electronic cloth in 2026, with the gap potentially widening further in 2027, alongside accelerating domestic substitution for high-end products.   In terms of A-share market opportunities, investors may prioritize leading electronic cloth manufacturers with ample capacity and a high-end product mix, while also keeping an eye on domestic substitute candidates that have achieved breakthroughs in Q-cloth technology. (Source: Everbright Securities Micro-Insights)   ------------------------------------------------------------- Source: Everbright Securities Micro-Insights Disclaimer: We respect originality and also value sharing; the copyright of text and images belongs to the original authors. The purpose of reprinting is to share more information, which does not represent the position of this account. If your rights are infringed, please contact us immediately for deletion. Thank you.

An 8-layer RF board built entirely on RO4350B will cost enough to make volume production unrealistic. Built entirely on FR-4, the 50Ω RF traces on the surface layer will not meet spec. Hybrid stackups are the way out. But hybrid construction is far more difficult to process than a single-material stackup—CTE mismatch causes delamination, multilayer lamination causes layer misregistration, and alternating thick and thin dielectrics make impedance hard to hold. We recently manufactured an 8-layer RO4350B + MT40 hybrid RF board that is a typical example of this design approach. This article is not just about how the board was built. It is about a question that comes up constantly at the material selection stage: when is a hybrid stackup worth it, and when is it not. The Board Specifications 8-layer copper construction. The top and bottom layers use 0.168mm RO4350B high-frequency material. The inner layers use 0.381mm MT40, a standard high-Tg FR-4 material, with 0.1245mm MT40 prepreg between layers. Finished outer copper is 1oz, inner copper is 0.5oz, and the laminated thickness is 1.636mm. Green solder mask, white silkscreen, palladium gold finish, 179mm × 121mm. The board includes L1-L2 and L7-L8 blind vias. The top layer carries 6mil single-ended traces with a 50Ω target impedance. Why RO4350B on the Surface, MT40 in the Middle The stackup logic is clear: high-frequency performance on the surface, structural support and cost control in the middle. The surface layers use RO4350B because that is where the RF traces are. RO4350B has a dielectric constant of about 3.48 and a dissipation factor of about 0.0037. Low Df means low dielectric loss, so microwave signals attenuate less as they travel along the surface. The 6mil single-ended 50Ω traces on the top layer are built directly on RO4350B, which gives tighter impedance control. The trade-off: RO4350B costs far more than standard FR-4. The inner layers use MT40 because power and ground planes do not need high-frequency performance. MT40 is a standard high-Tg FR-4 material, far cheaper than RO4350B. Its job is to provide structural support and thermal stability for the multilayer stack. If the inner layers also used RO4350B, material cost would rise sharply—and the power and ground planes do not need low Df. The trade-off: MT40's electrical performance is not as good as RO4350B, but used on inner layers it does not affect RF performance. The 0.1245mm MT40 prepreg controls interlayer thickness. Prepreg thickness directly affects the dielectric thickness between layers, which in turn affects impedance. The 0.1245mm specification was chosen to match the RO4350B and MT40 core thicknesses and hold the total laminated thickness at 1.636mm. The core logic of this stackup: high-frequency performance only where it is needed. Resource utilization is higher, and cost is more controllable. The Process Challenges: Three Real Problems Hybrid dielectric stackups are far harder to process than single-material stackups. This board had three main challenges. Challenge 1: CTE Mismatch Causes Delamination and Warpage RO4350B is a ceramic-filled material, and its CTE differs from MT40, which is FR-4 based. During lamination, the two materials expand at different rates, generating stress at the interface that can cause delamination or board warpage. The fix is a staged temperature ramp with slow cooling. The ramp is divided into multiple stages, each held long enough for the material to soften and flow fully. The cooling stage controls the rate of temperature drop to avoid internal stress from rapid cooling. This lets the two materials gradually accommodate each other's thermal expansion behavior during lamination, reducing interface stress. Challenge 2: Layer Misregistration After Multilayer Lamination A laminated thickness of 1.636mm is moderately thick for an 8-layer board. During multilayer lamination, registration accuracy between layers can drift, causing misregistration. The fix includes additional alignment targets and optimized pressure uniformity on the lamination plates. Alignment targets provide a more accurate registration reference, while pressure uniformity ensures even force across the panel and reduces local shifting. Challenge 3: Alternating Thick and Thin Dielectrics Make Impedance Sensitive to Thickness Variation The stackup alternates thick and thin: 0.168mm RO4350B, 0.381mm MT40, 0.1245mm prepreg. The thickness differences between dielectric layers are significant. Impedance is highly sensitive to dielectric thickness, and variation translates directly into impedance shift. The fix is tight incoming material thickness tolerance. RO4350B and MT40 core thickness, as well as prepreg thickness, must be strictly inspected at incoming inspection to ensure batch-to-batch consistency. Post-lamination dielectric thickness also needs to be verified by cross-section to confirm impedance stays within design range. The Cost Advantage Over an All-RO4350B Stackup The core value of a hybrid stackup is reducing cost while preserving high-frequency performance. This board's cost advantage shows up in three ways. First, material cost drops significantly. Replacing RO4350B with MT40 on the inner layers cuts material cost sharply. RO4350B is priced far above standard FR-4, and an 8-layer board built entirely on RO4350B would be very expensive. A hybrid stackup keeps RO4350B only on the surface layers, making it suitable for volume production of medium-to-large RF modules. Second, MT40's heat resistance compensates for the thermal reliability weakness of pure ceramic materials. MT40 is a high-Tg FR-4 material with good heat resistance and can survive multiple SMT reflow cycles. RO4350B offers excellent electrical performance, but its thermal reliability under repeated reflow is not as good as FR-4. Using MT40 in the inner layers improves the board's overall thermal reliability. Third, resource utilization is higher. High-frequency performance is only needed on the signal surface layers. Power and ground layers do not need low-Df material. Putting RO4350B where it counts and MT40 in the inner layers is a more rational allocation of resources. When You Should Not Use a Hybrid Stackup This is the part most stackup write-ups skip, and it is the most useful part for engineers at the material selection stage. If the entire board needs high-frequency performance. If inner layers also carry RF traces, or if power layers have strict impedance requirements, the hybrid advantage disappears. In that case, an all-RO4350B or other high-frequency stackup is more suitable. If the board is small. When material cost is a small share of total cost, the savings from hybrid construction are limited while process complexity increases. A single-material stackup may be simpler and more reliable for small boards. If multiple reflow cycles are not required. MT40's thermal reliability advantage only matters in multi-reflow assembly. If the assembly process is simple, that advantage goes unused, and the hybrid complexity is unnecessary. If cost is not the first constraint. If the project prioritizes performance far above cost, an all-high-frequency stackup avoids the process risk that hybrid construction introduces. The value of hybrid is balance—if you do not need balance, you do not need hybrid. The Bottom Line An 8-layer RO4350B + MT40 hybrid stackup is not a general-purpose solution. It is a targeted solution: it earns its process complexity when high-frequency signals are confined to the surface layers, the board is large, cost is sensitive, and multiple reflow cycles are required. The core logic is: high-frequency performance on the surface, structural support and cost control in the middle. The process challenges—CTE mismatch, layer misregistration, impedance variation—all have countermeasures, but those countermeasures add process complexity. If your design does not meet those conditions, a single-material stackup may be the more sensible choice. If you are working on an RF module stackup and need to balance performance against cost, we would be glad to review your requirements. Stackup decisions should start from your frequency, impedance targets, and cost goals—not from which material sounds best. Have you built hybrid stackups? What process issues did you run into?

Most RF boards are chasing thinner profiles. Thinner means lower module height, smaller parasitic effects, and tighter integration. But some designs go the other way. They call for a 2mm finished thickness on a 2-layer stackup. This is not a design mistake—it is a deliberate choice. When mechanical rigidity, plated through-hole reliability, and thermal stability matter more than height, a thin board becomes the problem, not the solution. We recently built a TMM6 board that falls into this category. 45.5mm × 90mm, 2 layers, 2mm finished thickness, 53 components, 38 vias, 2 nets. This article is not just about how the board was built. It is about a question that often gets overlooked: why a thick board can be more reliable than a thin one in certain RF applications, and what trade-offs that thickness brings. The Board at a Glance Base material: Rogers TMM6. 2-layer rigid PCB. Dimensions: 45.5mm × 90mm, ±0.15mm tolerance. Minimum trace and space: 5/8 mils. Minimum hole size: 0.35mm. No blind vias. Finished thickness: 2mm. Outer copper: 1oz (35 μm). Via plating: 20 μm. Surface finish: HASL. No top silkscreen, no bottom silkscreen. No top solder mask, no bottom solder mask. 100% electrical test before shipment. IPC-Class-2. Gerber RS-274-X. The stackup is 35 μm copper / 1.905mm (75mil) TMM6 core / 35 μm copper. A few details stand out: the 2mm thickness, the absence of solder mask and silkscreen on both sides, and the HASL finish on an RF material. Why 2mm, Not Thinner Standard FR-4 boards are typically 1.6mm. This board is 2mm—25% thicker than the norm. In RF design, added thickness changes several things. Mechanical rigidity. A 2mm board resists flexing during assembly, handling, and long-term use. On a large board (this one is 90mm long), thin material can warp during reflow, causing component shift or solder joint cracking. A thick board is more stable. Plated through-hole reliability. One of TMM6's core positioning points is high plated through-hole reliability. The thicker the board, the higher the aspect ratio, and the harder it is to achieve uniform plating. But once a thick board is properly plated, the barrel is mechanically stronger and less likely to crack under thermal cycling. This board has 38 through-hole vias, plated to 20 μm. Thermal stability. A thick core has more thermal mass, which helps spread heat in power amplifier applications. TMM6's thermal conductivity is 0.72 W/mK, and combined with 2mm thickness, heat dissipation is better than a thin board. The cost. Thick boards are harder to drill, more expensive in material, and heavier. If a design does not need these properties, 2mm is waste. TMM6: High Dk Without the Processing Headache TMM6 is part of the Rogers TMM family, alongside TMM10 and TMM10i. Its dielectric constant is 6.0, sitting between FR-4 (~4.3) and TMM10 (9.2). What Dk 6.0 means. High Dk shrinks circuit dimensions. In filters, couplers, and matching networks, the same electrical performance can be achieved in a shorter physical length. For space-constrained RF designs, that is real value. What Df 0.0023 means. At 10GHz, this is lower than FR-4 but higher than pure PTFE. For power amplifiers, combiners, and filters, this loss level is acceptable. Thermal coefficient of Dk: −11 ppm/°K. This is unusually stable. As temperature changes, the dielectric constant barely moves, meaning filter center frequencies and impedance values stay consistent. For satellite communication and outdoor RF equipment that see wide temperature swings, this stability is a real advantage. CTE matched to copper (18/18/26 ppm/K). This is why TMM6 is positioned for high plated through-hole reliability. The dielectric and the copper plating expand at nearly the same rate, reducing the risk of plating cracks and delamination under thermal cycling. Processability. TMM6's other selling point: it does not require the special processes that PTFE materials demand. No sodium naphthalate treatment, no unusual drilling parameters, and all common PCB processes work. For manufacturers, that means shorter lead times and lower processing cost. Why No Solder Mask, No Silkscreen, and HASL This board has no solder mask and no silkscreen on either side, and it uses HASL as the surface finish. No solder mask is common in RF and microwave designs. Solder mask has dielectric properties that can shift impedance and affect tuning, especially at higher frequencies. Removing it eliminates that variable and exposes copper directly for consistent RF performance. No silkscreen follows the same logic—markings serve no electrical purpose, and on an RF board they can sometimes interfere with tuning or inspection. The HASL choice is worth discussing. On high-frequency materials, ENIG or immersion gold are more common because they are flatter and suit fine-pitch components. But this board uses HASL—hot air solder leveling. HASL is lower cost and offers good solderability. This board has 15 top-side SMT pads and 21 through-hole pads, and HASL supports standard assembly. If the design does not need ENIG's flatness or gold's wire-bonding capability, HASL is a reasonable choice. Here is a trade-off worth stating clearly: HASL's surface flatness is not as good as ENIG. For fine-pitch SMT components, HASL can introduce soldering defects. This board's minimum trace is 5/8 mils, but the pad spacing is not fine enough to require ENIG, so HASL works. If a future design needs finer spacing, the surface finish may need to be reconsidered. 38 Vias, 2 Nets: What This Board Is Doing 53 components, 36 pads, 38 vias, 2 nets. High via count with low net count is a pattern we have seen before. It usually means a grounded structure—via fencing, ground plane stitching, or a shielded transmission line. These vias are not routing signals; they provide grounding and shielding. 21 through-hole pads and 15 top-side SMT pads indicate mixed assembly. No bottom SMT pads, consistent with the bottom side serving as a ground plane or mounting surface. When TMM6 Is Necessary When high Dk and miniaturization are hard requirements. Dk 6.0 shrinks the physical size of filters, couplers, and matching networks. If space is constrained, this is real value. When plated through-hole reliability is critical. CTE matched to copper, plus the mechanical stability of a thermoset resin, gives TMM6 an advantage in high-reliability applications. The combination of a thick board and high-aspect-ratio vias demands more from plating quality, and TMM6's material properties help. When temperature stability matters. A thermal coefficient of Dk of −11 ppm/°K means consistent performance across wide temperature ranges. Satellite communication, outdoor equipment, and automotive radar benefit. When processability cannot be compromised. TMM6 does not require PTFE's special processes, so lead times are shorter and costs are more controllable. For designs that do not want to pay for material processing complexity, this is a real advantage. When You Should Not Use TMM6 If your frequency is low and loss requirements are not strict. At low frequencies, FR-4 may be entirely sufficient. TMM6's high Dk and low loss would be overkill. If you do not need 2mm thickness. A 2mm board brings processing difficulty and cost. If module height allows, a standard-thickness board is easier to process and cheaper. If you need the lowest possible loss. TMM6's Df is 0.0023—lower than FR-4 but higher than pure PTFE. If loss is the primary constraint, a PTFE-based material may be more suitable. If cost is the first constraint. TMM6 is a ceramic-filled thermoset material, priced above FR-4. In cost-sensitive applications with modest performance requirements, there is no reason to pay for performance you will not use. The Bottom Line TMM6 is not a general-purpose RF material. It is a targeted solution: it earns its premium when high-Dk miniaturization, plated through-hole reliability, and temperature stability all matter at the same time. The 2mm thickness is not thick for its own sake. It serves mechanical rigidity, thermal stability, and via reliability. If your design does not need those, a thin board with FR-4 may be the more sensible choice.   If you are working on an RF or microwave design and need to balance high Dk, low loss, and plated through-hole reliability, we would be glad to review your requirements. Material selection should start from your frequency, power, and mechanical constraints—not from which material sounds best. Contact us to discuss your next RF PCB project.

How do you fit stable GHz performance into a board the size of a thumbnail? For engineers working on RF front-ends, antenna feeds, and microwave modules, this is a daily challenge. Space shrinks, frequencies climb, and the margin for error disappears. This article uses a recently completed 2-layer high-frequency PCB — built on Rogers RT/duroid 6202, measuring just 42.36mm × 21.9mm — as a lens to examine the material, stackup, and manufacturing decisions that make compact RF designs work. The Core Trade-off: Size vs. Signal Integrity When a board is small, every design choice compounds. Trace widths shrink, which makes impedance control harder. Board thickness drops, which affects mechanical rigidity and via aspect ratios. Component density falls, but connector performance becomes proportionally more important. In compact RF design, the question is rarely "what's the best material?" It's "what's the right material for this frequency, this footprint, and this budget?" Getting that balance wrong means either paying for performance you don't need, or losing signal integrity you can't afford. Choosing the Right High-Frequency Laminate RT/duroid 6202 sits in a family of low-loss, low-Dk laminates with limited woven glass reinforcement. Understanding where it fits — and where it doesn't — is the first step in material selection. Dielectric Constant and Thickness One of the most important things to understand about 6202 is that its Dk varies with thickness. At 10GHz/23°C, the numbers break down like this: 0.005" laminates: Dk of 3.06 ±0.04 0.010" and 0.015" laminates: Dk of 3.02 ±0.04 0.020" and above: Dk of 2.94 ±0.04 This matters because impedance is a function of trace geometry and Dk. If you're designing a 50-ohm line on a 20mil substrate, you're working with Dk 2.94. If you switch to a thinner laminate without recalculating, your impedance will shift. For boards with 4/7 mil traces, that shift can be enough to break the design. Loss and Thermal Stability The dissipation factor of 6202 is 0.0015 at 10GHz/23°C. For context, standard FR-4 sits around 0.02 — more than an order of magnitude higher. In a compact RF chain where every fraction of a dB counts, that difference is significant. Thermal stability matters too. The thermal coefficient of Dk is 5 ppm/°C at 10GHz across -50 to +150°C. CTE is 15 ppm/°C in X and Y, 30 ppm/°C in Z (-55 to 288°C) — well matched to copper. Td is 500°C TGA. Thermal conductivity is 0.68 W/m/K. Moisture absorption is 0.04%, and the material is UL 94-V0 rated. Dimensional Stability: The Hidden Advantage Perhaps the most underappreciated property of 6202 is its dimensional stability: 0.05 to 0.07 mils/inch. This comes from the limited woven glass reinforcement in the material. Why does this matter? When you're etching 4/7 mil traces, small dimensional shifts during processing can push traces out of tolerance. Many materials require double etching to hit tight positional tolerances. With 6202, that extra step is often unnecessary — which means faster processing, lower cost, and fewer opportunities for error. Stackup Design for Compact RF Boards The board in this example uses a simple 2-layer stackup: Copper layer 1: 35 μm Rogers RT/duroid 6202 substrate: 20mil (0.508mm) Copper layer 2: 35 μm Finished board thickness is 0.6mm, with 1 oz (1.4 mils) copper on the outer layers. There are no blind vias. Via plating is 20 μm. Surface finish is ENIG. Why This Stackup Works For a 2-layer RF board, simplicity is a feature. A single dielectric layer means fewer impedance discontinuities, easier controlled-impedance routing, and simpler manufacturing. The 20mil substrate provides enough thickness for reasonable trace widths at 50 ohms, while keeping the overall board thin enough for compact enclosures. The choice of ENIG as a surface finish is also deliberate. ENIG provides a flat, coplanar surface — important for fine-pitch SMT assembly and reliable soldering. It also offers good corrosion resistance and a long shelf life compared to finishes like OSP or immersion silver. Single-Sided Processing This board uses top silkscreen (white) and top solder mask (green), but no bottom silkscreen or solder mask. This is a common approach in RF modules where the bottom side needs to make direct contact with a metal housing or heatsink. Eliminating solder mask on that side ensures proper thermal and electrical contact. Manufacturing Considerations for Fine-Feature RF Boards The construction details of this board tell a story about manufacturing precision: Minimum trace/space: 4/7 mils Minimum hole size: 0.4mm Finished board thickness: 0.6mm Via plating thickness: 20 μm 100% electrical test prior to shipment The Challenge of Thin Boards At 0.6mm finished thickness, this board is thin enough to flex during handling and processing. Thin boards are more prone to warpage during lamination and etching, which can affect registration and trace integrity. The dimensional stability of 6202 helps mitigate this, but process control still matters. Fine Traces on Thin Substrates A 4/7 mil trace/space on a 0.6mm board requires careful control of etching parameters. Over-etching can reduce trace width and change impedance; under-etching can cause shorts. The fact that 6202 often eliminates the need for double etching simplifies this equation considerably. Via Reliability With a 0.4mm minimum hole size and 20 μm plating thickness, via reliability is a function of plating uniformity and adhesion. For RF signals, via performance also affects ground return paths and signal launch quality. Proper via design — including adequate ground vias near signal transitions — is essential for maintaining signal integrity.     Applications That Demand This Approach RT/duroid 6202 is commonly used in: Phased array antennas Ground-based and airborne radar systems GPS antennas Power backplanes Commercial airline collision avoidance systems Beam forming networks These applications share common requirements: stable RF performance across temperature, low signal loss, and reliable operation in demanding environments. A compact 2-layer board like the one described here fits naturally into these systems, particularly where space is constrained and every dB of signal budget matters. Key Takeaways for Your Next RF Design 1. Match Dk to your stackup. Don't assume a laminate's Dk is constant across thicknesses. Verify the value for your specific substrate thickness before finalizing trace geometries. 2. Consider dimensional stability early. If your design uses fine traces, a material with low etch shrinkage can save you a processing step and reduce risk. 3. Keep 2-layer stackups simple. For many RF applications, a single dielectric layer with controlled impedance routing is sufficient. Multilayer stackups add complexity and cost without always adding performance. 4. Plan your surface finish around assembly. ENIG is a strong default for fine-pitch SMT and wire bonding. If your bottom side needs thermal contact, consider whether solder mask should be omitted. 5. Test 100% before shipment. For RF boards, electrical test is not optional. Open and short verification across all nets ensures that what you receive matches what you designed. Final Thoughts Compact RF design is a balancing act. Material properties, stackup choices, and manufacturing capabilities all interact. The board profiled here — a 42.36mm × 21.9mm, 2-layer RT/duroid 6202 design with 4/7 mil traces and ENIG finish — illustrates how these factors come together in practice. If you're working on a similar high-frequency design and want to talk through material selection, stackup options, or manufacturing feasibility, feel free to reach out. We're always happy to review Gerber files and discuss what's possible.

Most antenna material choices come down to a balance between loss, cost, and processability. But there is a class of designs where the balance point is not loss. It is PIM. Passive intermodulation is one of the hardest problems to deal with in base station antennas and satellite communication systems. Unlike insertion loss, it cannot be calculated out of a link budget. Unlike return loss, it cannot be seen during tuning. It is a new interfering frequency generated by nonlinearities in materials or contact points when high-power signals pass through passive components. If those frequencies land inside a receive band, base station sensitivity drops—and you often will not realize it at the design stage. We recently built a 2-layer F4BTME350 board with a finished thickness of just 0.3mm. It serves exactly this kind of application: PIM-sensitive, and height-constrained. But this article is not just about how well the board was built. It is about when F4BTME350 is necessary, and when it is overkill. The Board Itself The base material is F4BTME350, a 2-layer rigid PCB. Dimensions are 89.77mm × 45.16mm, held to ±0.15mm. Minimum trace and space is 6/8 mils, and minimum hole size is 0.25mm. No blind vias. Finished thickness is 0.3mm, with 1oz (35 μm) copper on the outer layers and 20 μm via plating. Surface finish is immersion gold. Top silkscreen is white, with no bottom silkscreen. Top solder mask is black, with no bottom solder mask. Every board is 100% electrically tested before shipment, built to IPC-Class-2, with artwork supplied in Gerber RS-274-X. The statistics: 12 components, 38 total pads, 9 vias, 2 nets. Not many pads—but each one has a clear job. This is a small, focused design, not a general-purpose board. The stackup is 35 μm copper, a 0.254mm (10mil) F4BTME350 core, and 35 μm copper. At 0.3mm finished, the board is roughly one-fifth the thickness of a standard 1.6mm FR-4 board. The core is only 10mil, so the board is noticeably flexible, and warpage and handling damage need careful control during processing. The Real Value of F4BTME350: PIM F4BTME350 has a dielectric constant of 3.5 and a dissipation factor of 0.0025 at 10GHz. Those numbers are not extreme on their own—the Dk is slightly lower than FR-4, and the Df is better than standard FR-4 but not as low as pure PTFE. What makes it hard to replace in base station antenna and satellite communication applications is its PIM performance: ≤ -160 dBc. That number needs context. At 1900 MHz, a well-designed antenna typically targets PIM between -150 and -155 dBc. At -160 dBc, the material's own PIM contribution is pushed down to a level that is effectively negligible. The key to achieving this is the copper foil. F4BTME350 uses reverse-treated copper foil (RTF) rather than standard electrodeposited copper. RTF foil has lower surface roughness, and rough copper surfaces are a significant source of PIM. The F4BTM series uses ED copper and suits applications without PIM requirements; the F4BTME series switches to RTF foil specifically to minimize nonlinearity in PIM-sensitive designs. In other words, the premium you pay for F4BTME350 buys PIM, not Dk or Df. The Processing Reality of a 0.254mm Core A 10mil core is on the thin side for the F4BTME family. At this thickness, the board's mechanical rigidity comes mainly from the copper layers and the subsequent solder mask and surface finish. The core itself provides limited structural support. The drilling challenge is the 0.25mm minimum hole size. On a 0.3mm finished thickness, this is roughly a 1.2:1 aspect ratio—not extreme, but on a thin board, support and chip evacuation during drilling need attention. All 9 vias are through-hole, and the 20 μm plating must be uniform across the hole walls under thin-board conditions. The surface finish is immersion gold. For RF boards, this is a safe choice—no nickel-layer loss problem like ENIG, good flatness, reliable soldering. Combined with F4BTME350's low-roughness RTF copper, immersion gold helps keep conductor loss low. The board has black solder mask on the top only, with none on the bottom. This is common in antenna boards: solder mask has dielectric properties that can affect RF trace impedance, and removing it on the bottom eliminates that variable while exposing copper for heat dissipation or grounding contact. Black top mask with white silkscreen provides enough contrast for assembly and inspection. No bottom silkscreen, because the bottom is typically a ground plane or mounting surface where markings serve no purpose. When F4BTME350 Is Necessary When PIM is the system-level limiting factor. Base station receive sensitivity is directly affected by PIM. If a -150 dBc material would raise the noise floor enough to degrade receive performance, then -160 dBc is not "better"—it is required. When height is hard-constrained. A 0.3mm finished thickness suits highly integrated antenna arrays or compact RF front ends. A thin board reduces overall stack height while maintaining electrical performance. When frequency and power are both high. Satellite communications, phased array antennas, high-power amplifiers—these applications are sensitive to both thermal stability and nonlinearity, and F4BTME350's CTE (10 ppm/°C in X, 12 ppm/°C in Y) and low thermal coefficient of Dk have real value under those conditions. When You Should Not Use It This is the part most material write-ups skip, and it is the most useful part for readers. If your design operates below 1 GHz. At low frequencies, PIM is usually not a system-level bottleneck. F4BTME350's -160 dBc specification is overkill. The F4BTM series with ED copper may be entirely sufficient at lower cost. If PIM is not a system-level concern. Not every RF board runs high power. Low noise amplifiers, small-signal receive chains, lab test boards—in these, PIM will not be the limiting factor, and paying a premium for it makes no sense. If you do not need 0.3mm. Thin boards are harder to process, with more complex yield control. If module height allows, a standard-thickness F4BTME board is easier to process, more cost-effective, and mechanically more reliable. Thin is not an advantage in itself—it only becomes one when height is constrained. If cost is the first constraint. F4BTME350's RTF copper and low-PIM formulation make it a premium material. In cost-sensitive applications where PIM requirements are modest, standard FR-4 or the F4BTM series is the more reasonable engineering choice. The Bottom Line F4BTME350 is not a general-purpose antenna material. It is a targeted solution: it earns its premium when PIM is the limiting factor in your link budget, and when height must be compressed to the 0.3mm level. If your design does not meet both conditions, you are likely paying for performance you will never use.

Antenna boards are a different breed of PCB. On a digital board, the substrate is largely a mechanical carrier. On an antenna board, the substrate directly shapes how the circuit radiates, how much signal it loses, and how reliably it performs in the field. Get the material wrong, and no amount of layout skill will save the design. This article breaks down a recent 2-layer AD250C antenna board we manufactured—compact, ultra-thin, and finished with pure gold. Beyond the construction and stackup, we want to dig into a question that often gets overlooked: why did this board use pure gold instead of the more common ENIG, immersion silver, or OSP? What the Board Looks Like Let's start with the full specification. The base material is Rogers AD250C, a 2-layer rigid PCB measuring 55.36mm × 76.2mm, held to a tolerance of ±0.15mm. Minimum trace and space is 4/6 mils, and minimum hole size is 0.4mm. There are no blind or buried vias—all connections are through-hole. Finished board thickness is 0.6mm, with 1oz (35 μm) copper on the outer layers and a via plating thickness of 20 μm. The surface finish is pure gold. Top silkscreen is yellow, with no bottom silkscreen. Green solder mask is applied on both sides. Every board undergoes 100% electrical testing prior to shipment, built to IPC-Class-2, with artwork supplied in Gerber RS-274-X format. A few parameters stand out immediately: the 0.6mm ultra-thin thickness, the pure gold finish, and 49 vias on a board with only 2 nets. The Stackup: Thin by Design The stackup is straightforward: 35 μm copper, a 0.508mm (20mil) AD250C substrate, and 35 μm copper. The finished thickness is 0.6mm—roughly half that of a typical 1.6mm FR-4 board. Thin antenna boards serve two purposes: they reduce overall module height in space-constrained devices, and in certain patch and planar antenna designs, reduced dielectric loading can improve radiation efficiency. But thin boards bring manufacturing challenges. At 0.6mm, the board is more flexible, demanding greater care during drilling, plating, and assembly. Warpage control is especially critical with a core that is only 20mil thick. Why AD250C AD250C is a glass-reinforced, PTFE-based antenna laminate from Rogers, designed specifically for the wireless antenna market—cellular infrastructure base stations, automotive telematics, and commercial satellite radio. Its key electrical specs: dielectric constant of 2.5 ± 0.04 at 10GHz, dissipation factor of 0.0013 at 10GHz, and PIM of −159 dBc at 30 mil, 1900 MHz. Low Dk and antenna geometry. A Dk of 2.5 is far lower than FR-4's roughly 4.3. In antenna design, a lower Dk means the electromagnetic field extends further into the air rather than concentrating in the substrate. This generally improves radiation efficiency and reduces energy trapped in the dielectric. It also allows antenna elements to be sized closer to free-space wavelengths, simplifying matching and broadening bandwidth. Low Df and loss. A dissipation factor of 0.0013 is exceptionally low. FR-4 ranges from 0.012 to 0.020—roughly ten times higher. At antenna frequencies, this difference translates directly into reduced insertion loss and improved gain. The material's loss tangent stays below 0.002 across typical wireless bands, making it suitable for multi-band designs. Low PIM and antenna performance. Passive intermodulation is a critical spec for cellular infrastructure antennas. When two or more signals mix in a passive component, they generate intermodulation products that interfere with receive bands. AD250C's −159 dBc helps minimize this effect, reducing yield loss from PIM-related failures in production. Dimensional stability. CTE is 47 ppm/°C in X, 29 ppm/°C in Y, and 196 ppm/°C in Z. The glass-reinforced construction constrains in-plane movement, which matters for antenna arrays where element spacing must be precise. Surface Finish: Why Pure Gold, Not ENIG, Immersion Silver, or OSP This is the most interesting design decision on this board. Surface finish on an antenna board is not a casual choice. It directly affects three things: RF loss, PIM performance, and long-term reliability. Let's walk through each option. ENIG: The Nickel Layer Is a High-Frequency Killer ENIG's structure is copper → nickel (3–6 µm) → gold (0.05–0.1 µm). The gold layer is thin; the nickel beneath it does the real work. But nickel is ferromagnetic, with resistivity more than four times that of copper. At high frequencies, skin effect pushes current to the conductor surface. At 28 GHz, copper's skin depth is only about 0.4 µm—and ENIG's nickel layer is more than ten times that. The signal is effectively trapped in a highly lossy nickel layer. In measurements, a 28 GHz antenna using ENIG shows 0.7–1.2 dB lower efficiency than bare copper. ENIG is good for soldering. It is not good for RF. OSP: Great RF, Too Short-Lived OSP forms a film directly on copper, with no nickel layer, giving excellent RF performance—loss second only to ideal copper. But it has two hard problems. First, OSP is an insulator. If an antenna board has test points or requires probe contact, OSP causes poor contact and false open-circuit reports. Second, shelf life is only 3–6 months, and every reflow consumes the film. On a double-sided assembly or a board undergoing multiple thermal cycles, the OSP on the bottom side begins degrading after the first reflow, and the second soldering pass becomes risky. Antenna boards are often long-deployment products, and OSP's short life does not match that reality. Immersion Silver: The Sweet Spot for Antenna Boards Immersion silver deposits directly on copper, with no nickel barrier, at a thickness of only 0.15–0.4 µm. Silver's resistivity is only slightly higher than copper, so high-frequency signals travel on a surface that is close to bare copper. In measurements, immersion silver's antenna efficiency is only 0.1–0.2 dB below bare copper—far better than ENIG. The trade-off is storage. Silver tarnishes and sulfides, requiring sealed, moisture-controlled packaging. Shelf life is 6–12 months. Immersion silver's position: RF performance close to bare copper, moderate cost, suitable for most antenna applications. Pure Gold: Why This Board Chose It Pure gold also avoids the nickel-layer loss problem, but its value goes further. Extremely low PIM. One of AD250C's core selling points is PIM as low as −159 dBc. PIM is highly sensitive to surface condition: metal oxides, rough surfaces, and dissimilar metal interfaces all become nonlinear sources. Pure gold is chemically inert, smooth, and resistant to oxide formation, reducing PIM at the source. ENIG's nickel layer is itself a dissimilar metal that can contribute additional nonlinearity; tarnished silver can also degrade PIM. Long-term reliability. Base station antennas operate for years, deployed outdoors through thermal cycling and humidity. Pure gold does not oxidize, sulfide, or discolor, and contact resistance stays stable over time. OSP films degrade over time, and silver tarnishes. For an antenna that is installed and left alone, gold's reliability premium is worth paying. Compatibility with soldering and bonding. This board has 27 top-side SMT pads and 24 through-hole pads. Pure gold supports reliable soldering and also supports wire bonding. If a design includes direct chip attachment, pure gold is one of the few finishes that handles both. The trade-off is cost—the highest of the options. What it buys is the lowest PIM risk plus the longest reliability. Other Construction Details 4/6 mil trace and space. For an antenna board, this resolution is typically used for matching networks, feed lines, and tuning structures. AD250C's glass reinforcement improves processability and dimensional stability during etching, making this precision achievable. 49 vias, 2 nets. This is one of the more interesting details. A high via count with few nets in an antenna design usually indicates a grounded structure—a via fence, ground plane stitching, or an edge-grounded slot antenna. These vias are not routing signals; they provide shielding and grounding. The board carries 24 through-hole pads and 27 top-side SMT pads, mixing connector and component types. There are no bottom-side SMT pads, consistent with a design where the bottom serves primarily as a ground plane or mounting surface. 0.4mm minimum hole size. This is moderate rather than the finest possible, but it is a sensible choice for a 0.6mm thin board. Smaller holes on thin material risk drill breakage and uneven plating. The 20 μm via plating ensures barrel integrity. Solder mask and silkscreen. Green solder mask on both sides, with yellow silkscreen on the top only. No bottom silkscreen is typical when the bottom side is a ground plane or mounting surface where markings serve no purpose. Yellow on green provides good contrast for assembly and inspection. Quality and Delivery This board was manufactured to IPC-Class-2 standards, with 100% electrical testing prior to shipment to confirm net integrity and isolation. Artwork was supplied in Gerber RS-274-X, and the capability is available worldwide. What This Board Tells Us This AD250C build is a good example of how antenna boards differ from general-purpose PCBs. The material choice—driven by Dk, Df, and PIM requirements—sets the electrical foundation. The 0.6mm thin construction supports compact module integration. The pure gold finish protects surface conductivity while minimizing PIM risk. And the high via count on a low-net design reflects the grounded structures typical of antenna layouts. If you are working on an antenna design and need a manufacturer experienced with Rogers AD250C and similar PTFE-based laminates, we would be glad to review your requirements. Whether it is a simple patch antenna or a multi-element array, the conversation starts with your electrical and mechanical constraints. Contact us to discuss your next antenna PCB project.